1. Field of the Invention
The present invention relates to the field of processing semiconductor wafers for subsequent fabrication into semiconductor and integrated circuit devices. More particularly the present invention relates to a method whereby a semiconductor wafer may be prepared in the form of a thin epitaxial crystalline layer formed upon one or more thin insulative layers which in turn are supported on a substrate.
2. Discussion of the Prior Art
There has been an increased interest in the fabrication of devices incorporating thin layers of monocrystalline silicon as the active semiconductor region, i.e., the region wherein the semiconductor devices are formed. These layers are disposed on a supporting substrate -- typically an electrical insulator such as sapphire. Such composite wafers have been referred to as SIS wafers or where sapphire is the specific substrate material, SOS wafers. One of the particular interests in SIS wafers has been in regard to lateral devices wherein the diffused regions are formed throughout the entire thickness of the thin monocrystalline film. The diffused regions are placed adjacent to each other in such manner that the resulting junctions are formed in planes which are perpendicular to the plane of semiconductor wafer rather than in a plane parallel to the wafer surface as is substantially the case in standard planar technology. The beneficial result achieved by the use of lateral devices is a decrease in the capacitance of the diffused junctions which results in improved high frequency characteristics. In addition because of the potential for greater densities there is expanded interest in forming MOS or FET devices in SIS substrates by planar technology.
The prior art has developed three basic modes in which such SIS or SOS wafers may be fabricated. The first mode involves the pyrolitic deposition of silicon on a sapphire or spinel substrate. By careful control of the quality of the substrate's surface, a single crystal film of 1 to 10 microns thickness can be grown. The chief disadvantage of silicon films grown on sapphire or spinel substrates has been the poor quality of crystalline perfection usually obtainable in such films. The extent of crystalline imperfection has in fact been so great as to substantially disqualify wafers made by this mode for use in bipolar devices and dynamic MOS devices.
A second mode of fabrication of the prior art involves the use of an anodic dissolution of a parent substrate. More specifically, this mode involves the use of a heavily doped, substrate of silicon upon which an epitaxial layer of less highly doped silicon has been disposed. The epitaxial silicon layer and the underlying parent substrate are then partially oxidized and a thick layer of polycrystalline silicon is then formed upon the oxidized surface. The epitaxial layer of silicon forms the middle of a sandwich between the polycrystalline silicon and the oxidized layer on one side, and the parent substrate on the other side. The final step of this method is then to anodically dissolve the parent substrate. The result is a SIS type structure consisting of a monocrystalline epitaxial layer of silicon on a thin layer of silicon oxide supported in turn by a thick layer of polycrystalline silicon. The crystalline perfection of the epitaxial layer grown by this method is significantly greater than that grown by the method utilizing spinel or sapphire as a parent substrate.
A third method of the prior art has modified the anodically fabricated SIS wafer by substituting a field assisted bonding step in place of the deposition of polycrystalline silicon. More particularly, this third method begins with a substrate of heavily doped monocrystalline silicon upon which an epitaxial layer of less heavily doped silicon has been grown. As in the previous method, the epitaxial layer is then provided with a thermal oxide coating, but in place of the step of depositing polycrystalline silicon described above, a second substrate of monocrystalline silicon, similar to the substrate upon which the epitaxial crystalline layer was grown, is prepared and provided with a thin oxide coating. The oxide coating of the second substrate is then bonded to the oxide coating covering the epitaxial layer. The bonding process utilized is known as field assisted bonding. The field assisted bonding process is well known in the art as that method is employed to bond glass to metal by use of a combination of heat and electrostatic pressure. See G. Wallis and E. I. Pomerantz, 40 J. Appl. Phys. 3946 (1969); G. Wallis, 53 J. Am. Ceram. Soc. 563 (1970); P. B. DeNee, 40 J. Appl. Phys. 5396 (1969). Typically this method involves placing the silicon oxide layers of the two substrates on top of each other and heating them to about 900.degree. C. A voltage of about 100 volts (for 2 microns of oxide) is then applied across the heated wafer and maintained for a few minutes. The combination of the electrostatic force from the applied voltage and the heat produces a bond with a tensile strength between 500-1000 psi. As a general rule the bonding is uniform across the oxide surface provided that the bonded surfaces are smooth, flat and free of pinholes.
The next step in the method utilizing the field assisted bonding process is the removal of the parent substrate upon which the epitaxial layer was grown. Numerous methods exist in the prior art by which the parent substrate may be thinned or removed to expose the epitaxial silicon layer. After removal of the parent layer the resulting structure is an epitaxial layer disposed upon a double layer of silicon oxide which in turn is supported by a thick crystalline substrate. This SIS type wafer has several advantages over the wafer fabricated utilizing polycrystalline silicon as the underlying substrate, which advantages include the substantial identity of the thermal coefficient of the underlying substrate with that of the epitaxial layer. Where a SIS is fabricated with a polycrystalline supporting substrate, the thermal coefficient may be of such disparity that substantial warping of the composite wafer could occur during subsequent processing steps.
Another advantage associated with the field assisted bonding method results from the application of lower temperatures during the bonding step whereby outdiffusion and autodoping from the heavily doped parent substrate is reduced and contamination of the epitaxial crystalline layer substantially prevented.
Since the epitaxial layer may be as thin as 1-4 microns, the final thinning and removal process of the parent layer is a critical step. Great care must be taken during the dissolution of the parent layer in the field assisted bonding process so that the etching may be stopped just at the epitaxial layer. Such control is difficult to achieve. What is needed then is a process for fabricating SIS wafers utilizing a controllable thinning process in which the removal of the parent layer and the exposure of the epitaxial layer can be immediately and accurately detected and controlled.